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This new IP core from Xylon logicBRICKSTM IP library is a hardware-enabled 3-D graphics engine IP core developed for embedded systems based on Xilinx FPGA technology. The logi3D enables deployment of high quality 3-D graphics in resource- and cost-constrained embedded systems serving most demanding computer graphic applications, i.e. automotive navigation systems. Modern FPGA devices providing abundance silicon resources have already changed embedded systems design paradigm. The logi3D is a parametrizable and scalable IP core that perfectly fits to other logicBRICKSTM IP cores, allowing advanced and highly customized graphic controller designs. This scalable approach enables an exact match of customer requirements and enabled IP features. Eventually customers set up an exact systems’ performance level and pay only for what they need. The logi3D has been designed to support widely adopted and modern graphics APIs for 3-D graphics applications. The IP is actually based on OpenGL® ES 1.1 API specifications. OpenGL® ES is a royalty-free, cross-platform API for full-function 2D and 3D graphics on embedded systems - including consoles, phones, appliances and vehicles. It consists of well-defined subsets of desktop OpenGL, creating a flexible and powerful low-level interface between software and graphics acceleration. About OpenGL®
ES
Functional Description The logi3D IP core implements a standard graphics rendering pipeline architecture characteristic for this type of HW accelerators. There are three successive stages: geometry, rendering and post-filtering stage. Input 3-D vertices and textures are fed to these IP’s stages by the system CPU running the 3-D software application, and a resulting rendered 3-D scene is stored in video controller’s frame buffer. The resulting 3-D scene can be displayed on a single or multiple LCD/CRT displays. - System CPU Interface Input 3-D data and logi3D control commands are received through a system CPU interface. These data are formatted in accordance to the OpenGL® ES 1.1 API specifications. The system CPU interface can be tuned for different CPU types in ways that assure optimal FPGA implementation and a high communication speed. A host/client connection between the system CPU and the logi3D is controlled by software that is a standard part of IP’s deliverables. In ultimate System-on-Reprogrammable-Chip (SoRC) configurations, the system CPU can be the Xilinx MicroBlaze RISC processor. - The Geometry Stage This is a very complex 3-D engine’s stage that executes per-polygon and per-vertex operations including complex math operations. Its sub-stages can be generally nominated as: model view, lighting, projection, clipping and screen mapping. A pure HW implementation of the geometry stage would be too costly within the FPGA from the slice consumption point of view. The logi3D IP core’s geometry stage is carefully HW/SW partitioned for optimum execution speed and FPGA slice consumption. A majority of necessary 3-D transformations are executed by a dedicated Xilinx’s MicroBlaze 32-bit RISC soft-CPU. The Microblaze’s speed of execution is increased by a number of HW modules dedicated to time-consuming transformations, i.e. matrix multiplier, frustum calculator. These HW modules are connected to the MicroBlaze by the Fast Simplex Link (FSL) bus and act as natural CPU’s extensions. Processor data and instruction memories are implemented in the common SDRAM-type memory used for logi3D operations. - The Rendering Stage The rendering stage does per-pixel operations. It resolves pixel elements’ colors by a mean of the color-buffer with an associated Alpha channel. The renderer checks visibility of various objects (oculsion culling) within the 3-D scene and resolves it by a mean of the Z-buffer. A level of the 3-D scene’s realism
is further increased by texturing that is actually “gluing”
of images onto 3-D objects. The logi3D enables various modes of texture
operations especially tailored for Xilinx FPGA operations. The fastest
texturing can be achieved by textures that fit into Xilinx on-chip Block
RAM memory modules. Besides, the logi3D enables textures storage within
the common memory, and the mipmapping. - The Post-Filters Stage This final stage enables 4X full rendered 3-D scene anti-aliasing. Beside the anti-aliasing that smoothes the 3-D graphics, a number of other post-filters is available, i.e. fog. This stage’s output is the final 3-D
picture prepared for one or more 2-D LCD displays. The picture must be
sent to display(s) by dedicated video controllers. logi 3-D Design Flow logiCRAFT2 3-D Demo System
The logi3D Scalable 3-D Graphics Accelerator can be evaluated on the logiCRAFT2 Multimedia and Infotainment Evaluation/Development platform designed by Xylon. A reduced block diagram above presents major parts of the 3-D demo FPGA design based on Xilinx and Xylon IP cores. The design is a primer example of a 3-D graphics system fully integrated into a single FPGA device. Two Xilinx MicroBlaze CPUs runs at the same time within this multi-CPU Spartan-3 design: the system CPU, and the CPU within the logi3D IP core’s geometry stage. The System CPU runs SW demo application controlling
examples of 3-D menus and navigation examples. The SW demo application
feds the logi3D Graphics Accelerator that renders the 3-D graphics and
stores it into frame buffers. Xylon logiCVC-ML Compact Multilayer Video
Controller displays the resulting graphics on attached LCD display or
CRT monitor. Availability The logi3D evaluation is available trough an early access program. The release date logi3D is planed for the end of February, 2007. DISCLAIMER
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> logi3D
– Scalable 3-D Graphics Accelerator
