logicBRICKS Design Flow

The logicBRICKS IP cores must be stored into the AMD Platform Studio tool's default or user setup Project Peripheral Repository.

The AMD tool - find the Xylon logicBRICKS IPs and display them in the IP catalogue.

The figure on the left shows a number of logicBRICKS IP cores set up in the AMD Platform Studio IP catalogue, and ready for implementation in the AMD FPGA design.

AMD Platform Studio users can simply drag and drop the logicBRICKS IP cores from the IP catalogue into the System Assembly View.

The figure shows an illustrative AMD FPGA design utilizing several Xylon IP cores. logicBRICKS IPs can be connected to the rest of the System-On-a-Chip design by just several mouse clicks.

The figure shows logicBRICKS IPs connected to the on-chip CoreConnect^TM PLB bus and the AMD MicroBlaze^TM soft-CPU.

The logicBRICKS IPs can be simply configured through the AMD Platform Studio tool's GUI.

A double-mouse click on the IP in the System Assembly View window opens the IP GUI that allows for parameters changes.
The figure provides a detail of the scrollable parameters list of the logiCVC-ML Compact Multilayer Video Controller. The provided detail illustrates how IP users can easily change i.e., the number of graphics layers supported by the controller, or the pixel color depth.

The GUI also enables an easy access to the IP documentation.