- Fundamental building block for FPGA based automotive Rear Looking Lane Departure Warning System
- Supports Xilinx® Zynq®-7000 All Programmable SoC and Zynq UltraScale+ MPSoC
- ARM® AMBA® AXI4-Stream compliant video input
- AXI4-Lite compliant registar interface
- Adapts to shadows and light changes
- Hough Transform based model fitting
- Implements the most computing demanding tasks in programmable logic
- High Input Data Rate; > 200 Mpixel/sec
- Customizable input image dimension (default 800x600)
- Supported video stream formats: RGB(8:8:8), YUV(4:4:4) and YUV(4:2:2)
- Provides high level decision making reasoning as open source embedded software
- Prepackaged for Xilinx Vivado® Design Suite
- If you are interested in FPGA implementation, please contact Xylon
The logiLMD Lane Marking Detection IP core from Xylon's logicBRICKS IP core library is designed to detect the lane markings on the roadway video scenarios captured from a rear-view camera, and to raise an alert in case the host's vehicle departs from the lane. Its functions include image-processing filters, like Gaussian smoothing and Edge detection, and blocks specifically tailored for lane marking detections. The output of the core is the set of straight lines corresponding to lane markings.
| The logiLMD core is sourced from Technology Partner
eVS embedded Vision Systems Srl.