Xylon announces new generation of its Memory Controller IP core

Xylon is proud to release the newest iteration of our storied - logiMEM - DDR3 SDRAM Memory Controller IP Core. The logiMEM IP Core is a size optimized, flexible, parametric and synthesizable Synchronous DRAM Controller that now supports the industry standard Double Data Rate 3 (DDR3) SDRAM memories.

As with each major update to it before, this new iteration is specifically prepared for use the with the modern generation of AMD-Xilinx 7-series families. In comparison to Xilinx Memory Interface Generator (MIG 7 Series) IP, Xylon’s logiMEM has an extremely small footprint and allows for 3x-5x savings of programmable logic thanks to its its carefully selected features subset.

The logiMEM IP Core will be again offered through Xylon's logicBRICKS Low-Volume IP Program.


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