IP Cores - logiMEM

SDR/DDR SDRAM Memory Controller

Key Features

  • Try Before Buy - No cost and no obligation!
  • Supports SDR and DDR SDRAM memory types
  • 16/32-bit DDR SDRAM data interface
  • 32/64-bit SDR SDRAM data interface
  • 32/64-bit CoreConnectTM PLB slave system port
  • 32-bit CoreConnect OPB slave system port
  • 4 Xilinx® CacheLink (XCL) system ports for the Xilinx MicroBlazeTM cache interfacing
  • 10 Xylon Memory Interface (XMB) ports for the logicBRICKS interfacing
  • Configurable memory interface: Xylon XMB and CoreConnect PLB
  • Can support special memory interfacing requirements on request


The logiMEM SDR/DDR SDRAM controller, an IP core from Xylon logicBRICKS IP library, provides a powerful, yet simple-to-use interface between the industry standard memory devices and several processor(s) or on-chip peripherals. These peripherals can share and access the same physical memory devices through different system buses. The single logiMEM instance can support multiple system ports compatible with the PLB, OPB, Xilinx XCL and Xylon XMB bus. Written in generic VHDL, the logiMEM is extremely adoptable and can fit into high-end Xilinx SoRC (System on Reprogrammable Chip) systems, as well as into low-end systems featuring UMA (Unified Memory Architecture) system architecture. The core is fully embedded into Xilinx Platform Studio and EDK tools, and its integration with on-chip CoreConnect PLB and OPB buses is very simple. Parametrizable VHDL design allows tuning of slice consumption and features set through an easy-to-use GUI interface .
NameLicensePrice (EUR)  
logiMEM 1 year license 850.00
logiMEM 2 years license 1,530.00
logiMEM 3 years license 2,040.00
Related Products
Name Price (EUR)  
logiMEM-10K10K bitstreams
logiMEM-20K20K bitstreams
logiMEM-50K50K bitstreams
logiMEM-100K100K bitstreams
logiMEM-UNLAdditional unlimited bitstreams
Additional Products
Name Price (EUR)  
logiHELP 10 hours package900.00
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