SDRAM Memory Controller and Arbiter
The logiMEM_arb Memory Controller and Arbiter IP core is specially designed for AMD Spartan™ 6 FPGA memory interfaces. This IP core supports up to 16 IP ports, up to 8 simultaneous IP memory accesses and different on-chip bus standards: AMBA® AXI4, CoreConnect PLB, AMD Cache Link, AMD Native Port Interface and Xylon Memory Bus (XMB)
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1,020 EUR
- 1 year license
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1,840 EUR
- 2 years license
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2,450 EUR
- 3 years license