Enhanced 2D Graphics Accelerator Available

logiBITBLT IP core with enhanced features set and architectural improvements

> 31. January 2014, Zagreb (Croatia) – 
Xylon, a leading provider of advanced FPGA application solutions, logicBRICKS™ IP cores and design services, introduces its latest version of the logiBITBLT Bit Block Transfer 2D Graphics Accelerator IP core optimized for Xilinx® Zynq™-7000 All Programmable SoC and FPGAs. The logiBITBLT IP core is designed to speed up graphics processing and offload the host processor, and to enable easy system integration and development.

The latest IP version has an enhanced features set and improved performances. Introduced architectural improvements specifically target the 7 series Xilinx All Programmable FPGAs and the Zynq-7000 AP SoC. Xylon provides an extensive software support for different operating systems and graphics APIs to enable quick and efficient software development with popular graphics libraries and widget toolkits through industry standard design flows.

The logiBITBLT IP core transfers graphics objects from one to another part of system’s on-screen or off-screen video memory, and performs different operations during transfers, such as ROP2 raster operations, bitmap scaling, flipping, Porter & Duff compositing rules or transparency.

The logiBITBLT Bit Block Transfer 2D Graphics Accelerator is available in formats compatible with Xilinx Vivado IP Integrator and ISE Platform Studio implementation tools, along with complete reference designs for the most popular Xilinx Zynq-7000 AP SoC based evaluation kits.

The logiBITBLT Bit Block Transfer 2D Graphics Accelerator IP core license fees offered through Xylon's Low-Volume IP Program (LVIP) start at €2,900. For datasheet, please CLICK HERE.

Key features:

• Try Before Buy – available evaluation IP core with no cost and no obligation!
• Supports Xilinx® Zynq-7000 All Programmable SoC and FPGAs
• Available software drivers for different operating systems
• Supports 16 different ROP2 raster operations
• Porter & Duff compositing rules with/without global alpha
• Integrated bitmap flipping and optional up/down scaling
• Color keyed transparency and anti-aliased 8-bit font expansion
• Objects moves in positive and negative directions
• Control of pixel alpha blending factors
• Supported image formats: RGB8, ARGB8, RGB16, ARGB16, RGB24 and ARGB24
• ARM® AMBA® AXI4 and AXI4-Lite bus compliant
• Available for Xilinx Vivado® IP Integrator and ISE® Platform Studio
Free reference designs for popular development kits

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