Meet Xylon at FPGA-Kongress 2016

> 12. - 14. July 2016 – NH Hotel, Dornach-Műnchen (Germany)


Visit FPGA-Kongress website


The FPGA-Kongress is a forum for developers, users and research institutions. Organized by the magazine ELEKTRONIKPRAXIS and PLC2 GmbH company, which is Xilinx ATP (Authorized Training Provider), the event provides user-friendly and cross-vendor information on design methods, architectures, SW / HW embedded SoC, verification, and much more about FPGAs.

 
 
 
 

Xylon shall participate in the exhibition program with the live demonstrations of the company’s advanced Ultra-HD High Dynamic Range (HDR) Image Signal Processing (ISP) pipeline and vision-based ADAS systems. Also, Xylon shall give three presentations within the official congress program:

Advanced Real-Time Video Processing (Embedded Design Lane, 16:30 – 17:30, July 13)

Virtual reality, machine vision, advanced driver assistance and video surveillance mark an ever growing number of camera-based applications that require powerful video processors with a right level of performance, low latency and great flexibility in handling massive amounts of video data that usually come from multiple video sources. During this session, we shall demonstrate an advanced video processing IP core for real-time advanced video manipulations, such as the camera lens distortions removal, video rotations for an arbitrary angle, pre-warping, scaling and stitching of multiple video streams in a single display output image. An example multi-camera design will be demonstrated on the Xilinx Zynq-7000 AP SoC based ADAS hardware platform from Xylon.

Ultra HD Camera Interfacing, Video Capture and Display (Embedded Design Lane, 13:30 – 15:00, July 14)

Due to an ultimate IO flexibility, programmable FPGA and SoC devices present excellent hardware platforms for Ultra high definition (HD) video processing and development of next generation smarter vision applications. Designers working on such applications should have a good understanding of camera sensor video and control interfaces and SoC architectures that ensure performance suitable for smooth video frame grabbing and display output of 4K2K and higher resolution video inputs. An example design featuring 4K2K video camera will be demonstrated on the Xilinx Zynq-7000 AP SoC based reference hardware platform from Xylon.

Ultra HD Image Signal Processing (ISP) Pipeline (Embedded Design Lane, 15:30 – 17:00, July 14)

Assuring high quality video input for smarter vision embedded systems, from machines that see, to high-end broadcast cameras, requires implementation of Image Signal Processing (ISP) pipelines that digitally enhance the quality of input video streams. During this session, we shall describe the ISP application landscape, explain the theory of operation of the main ISP pipeline modules and present the Xylon Ultra HD ISP pipeline features. Video processing techniques, such as the High Dynamic Range, Auto White Balance, Auto Exposure, Local Tone Mapping and other, will be demonstrated on the Xilinx Zynq-7000 AP SoC based 4K2K reference hardware platform from Xylon.
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