IP Cores - logiISP-UHD

Image Signal Processing (ISP) UltraHD Pipeline

Key Features

  • Supports AMD Versal™ ACAP, AMD Zynq™ UltraScale+™ MPSoC, Zynq™ 7000 SoC, Series 7 and newer FPGAs
  • Complete and configurable ISP pipeline includes:
  • - Defective Pixel Correction
    - Color Filter Array Interpolation

    - Image Statistics (+ AWB & AE Support)
    - Color Correction Matrix
    - Gamma Corrections
    - Image Enhancement
    - Motion Adaptive Noise Reduction
    - YCbCr to RGB Color-Space Converter
    - RGB to YCbCr Color Space Converter
    - Chroma Resampler
  • Support parallel processing of multiple video channels
  • Digitally processes and enhances the quality of an input video stream and collects video statistics data for use in video control algorithms
  • Supports resolutions up to 7680x7680, including 4K2Kp60 (3840x2160)
  • Input video formats: Raw Bayer, RGB and YCbCr
  • Video input's bitwdith can be as wide as 20-bit per component
  • Parallel pixel processing of 1, 2 or 4 pixels per clock
  • Video Input and output are ARM® AMBA® AXI4-Stream protocol compliant
  • Optional registers are AMBA AXI4-Lite protocol compliant
  • The bit-accurate C model for evaluations available on request
  • Fee-based license extension for the AWB&AE
  • Available for AMD Vivado™ IP Integrator

Xylon offers the complete HDR ISP IP suite, evaluation kits and software - CLICK HERE to learn more. VIDEO CLIP!


The logiISP-UHD Image Signal Processing IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital processing and image quality enhancements of an input video stream in embedded designs based on AMD MPSoC, SoC and FPGA devices. The logiISP IP core accepts diversely formatted video inputs generated by different sensors and removes defective pixels, de-mosaics Bayer encoded video, makes image color and gamma corrections, filters the noise from the video, collects video analytics data for various control algorithms and manipulates video data formats and color domains. In addition to the standard IP core deliverables, Xylon offers licensable Auto White Balancing (AWB) and Auto Exposure (AE) processor-based control libraries that work with the video analytics data collected by the ISP pipeline. The two libraries are licensable as a software library bundle under the name logiISP-2A.

The logiISP IP core can be easily combined with the logiHDR High Dynamic Range (HDR) Pipeline IP core into advanced video processing pipeline capable to extract the maximum detail from high contrast scenes, i.e. scenes with objects highlighted by a direct sunlight and objects placed in extreme shades.

The logiISP Image Signal Processing Pipeline IP core is prepackaged for AMD Vivado™ IP Integrator (IPI) tool, requires no skills beyond general tools knowledge and can be used in same ways as AMD IP cores. Video system designers can easily setup the logiISP ISP pipeline configuration by selecting video input and output formats, switching on and off pipeline stages (blocks) and setting up all IP core’s parameters through an easy-to-use IPI GUI interface.


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