logiREF-VIDEO-ISP-EVK Image Signal Processing (ISP) Pipeline

Xylon's logiISP Image Signal Processing (ISP) Pipeline IP core is a full high-definition ISP pipeline designed for digital processing and image quality enhancements of an input video stream in smarter vision embedded designs based on Xilinx® Zynq®-7000 AP SoC and 7 Series FPGA devices.

The logiREF-VIDEO-ISP-EVK reference design allows the user to quickly evaluate and experiment with Xylon's ISP pipeline on the MicroZed™ Embedded Vision Development Kit from Avnet Electronics Marketing. This free and pre-verified design includes evaluation logicBRICKS IP cores and hardware design files prepared for Xilinx Vivado® Design Suite. It also includes the complete Linux OS image, software drivers, demo applications and documentation.


 
Xylon Image Signal Processing (ISP) Pipeline Demo runs on the Xilinx Zynq®-7000 All Programmable SoC based MicroZed™ Embedded Vision Kit from Avnet Electronics Marketing.

The original demo resolution is 1080p60. The presented compressed video has been captured by the frame grabber at 30fps.

The evaluation hardware design is customizable. logicBRICKS IP cores can be setup through the Vivado IP Integrator (IPI) and design users can evaluate different logiISP features, make changes on the logicBRICKS graphics sub-system and add third-party IP cores required by the target application.
 Block diagram of logicBRICKS Image Signal Processing (ISP) Pipeline demo for the MicroZed Embedded Vision Development Kit
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Download reference design built by evaluation logicBRICKS IP cores and run it and evaluate on your MicroZed Embedded Vision Development Kit.

You must be registered in order to get the logicBRICKS reference designs. The registration is free of charge and with no obligations. For quick information on how to register, install the design, get evaluation IP license and similar, please CLICK HERE!

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