Each logiCVC-ML layer that reads data from video buffer (not from external RGB input) has its starting address from which it reads data.
This address is set by configuring VHDL generic parameters C_VMEM_BASEADDR and C_LAYER_X_OFFSET.
C_VMEM_BASEADDR is the base address of the whole logiCVC-ML core.
logiCVC-ML can address a maximum of 256MB. However, there is one restriction on setting the base address C_VMEM_BASEADDR.
In order to reduce the slice consumption, user has to take care to set the base address in boundaries of the address range the logiCVC-ML will use.
For example, if logiCVC-ML uses 32MB of memory than the base address can be set only in boundaries of 32MB (C_VMEM_BASEADDR = 0x2000000, 0x4000000, ...)
Using C_LAYER_X_OFFSET parameters every layer can be configured to read from its own base address.
C_LAYER_X_OFFSET from C_VMEM_BASEADDR is represented in number of lines where each line can have different size.
For example, 1KB for 8bpp layer and C_ROW_STRIDE=1024,
2KB for 16bpp or 8bpp layer with pixel alpha and C_ROW_STRIDE=1024,
4KB for 24bpp or 16bpp layer with pixel alpha and C_ROW_STRIDE=1024,
8KB for 24bpp layer and C_ROW_STRIDE=2048.
C_LAYER_X_ADDRESS is calculated as C_LAYER_X_ADDRESS = C_VMEM_BASEADDR + C_LAYER_X_OFFSET*LAYER_X_WIDTH*C_ROW_STRIDE.
LAYER_X_WIDTH = 8 for C_LAYER_X_DATA_WIDTH = 8 and C_LAYER_X_ALPHA_MODE = 0, 2, or 3.
LAYER_X_WIDTH = 16 for C_LAYER_X_DATA_WIDTH = 16 and C_LAYER_X_ALPHA_MODE = 0 or C_LAYER_X_DATA_WIDTH = 16 and C_LAYER_X_ALPHA_MODE = 1.
LAYER_X_WIDTH = 32 for C_LAYER_X_DATA_WIDTH = 16 and C_LAYER_X_ALPHA_MODE = 1 or C_LAYER_X_DATA_WIDTH = 24.
C_BUFFER_X_OFFSET offset is relative to layer address offset represented in number of lines where each line can have different size, same as C_LAYER_X_OFFSET.
Additionally, offset register is used to move the starting point in memory from which the data will be read, i.e. the first pixel on display.
Display resoultion is 1024x768 (C_ROW_STRIDE = 1024) with dobule buffering for layer 0,1,3,4 and triple bufering for layer 2 and pixel alpha for layer 0 and 1.
C_LAYER_X_DATA_WIDTHs are as follows: 8, 16, 24, 8, 16.
C_BUFFER_X_OFFSET is for every layer 768.
C_LAYER_0_OFFSET is set to 0, i.e. the starting address is C_VMEM_BASEADDR.
C_LAYER_1_OFFSET is (2B*768*2)/4B = 768
C_LAYER_2_OFFSET is (2B*768*2 + 4B*768*2)/4B = 2304
C_LAYER_3_OFFSET is (2B*768*2 + 4B*768*2 + 4B*768*3)/1B = 18432
C_LAYER_4_OFFSET is (2B*768*2 + 4B*768*2 + 4B*768*3 + 1B*768*2)/2B = 9984
C_LAYER_0_ADDRESS is C_VMEM_BASEADDR.
C_LAYER_1_ADDRESS is C_VMEM_BASEADDR + 768 *4B*1024 = C_VMEM_BASEADDR + 3 MB.
C_LAYER_2_ADDRESS is C_VMEM_BASEADDR + 2304 *4B*1024 = C_VMEM_BASEADDR + 9 MB.
C_LAYER_3_ADDRESS is C_VMEM_BASEADDR + 18432*1B*1024 = C_VMEM_BASEADDR + 18 MB.
C_LAYER_4_ADDRESS is C_VMEM_BASEADDR + 9984 *2B*1024 = C_VMEM_BASEADDR + 19.5 MB.
Please notice that C_LAYER_X_OFFSET for a layer can be adjusted to a smaller value than C_LAYER_X_OFFSET for the layer beneath.
The C_LAYER_X_OFFSET values are calculated referring to the layer they are calculated for.
PARAMETER C_VMEM_BASEADDR = 0x10000000
PARAMETER C_VMEM_HIGHADDR = 0x10FFFFFF
PARAMETER C_NUM_OF_LAYERS = 5
PARAMETER C_ROW_STRIDE = 1024
PARAMETER C_LAYER_0_DATA_WIDTH = 8
PARAMETER C_LAYER_1_DATA_WIDTH = 16
PARAMETER C_LAYER_2_DATA_WIDTH = 24
PARAMETER C_LAYER_3_DATA_WIDTH = 8
PARAMETER C_LAYER_4_DATA_WIDTH = 16
PARAMETER C_LAYER_0_ALPHA_MODE = 1
PARAMETER C_LAYER_1_ALPHA_MODE = 1
PARAMETER C_LAYER_2_ALPHA_MODE = 0
PARAMETER C_LAYER_3_ALPHA_MODE = 0
PARAMETER C_LAYER_4_ALPHA_MODE = 0
PARAMETER C_LAYER_0_OFFSET = 0
PARAMETER C_LAYER_1_OFFSET = 768
PARAMETER C_LAYER_2_OFFSET = 2304
PARAMETER C_LAYER_3_OFFSET = 18432
PARAMETER C_LAYER_4_OFFSET = 9984
PARAMETER C_BUFFER_0_OFFSET = 768
PARAMETER C_BUFFER_1_OFFSET = 768
PARAMETER C_BUFFER_2_OFFSET = 768
PARAMETER C_BUFFER_3_OFFSET = 768
PARAMETER C_BUFFER_4_OFFSET = 768