logiCVC doesn't read memory until the first write to DTYPE register after a reset is issued (FPGA bitstream download or register interface reset).
Additionaly, every logiCVC layer has its own LX_CTRL register. Bit 0 of LX_CTRL enables layer X to read data from memory. By default and after reset, only layer 0 has this bit set to 1. All other layers need to be enabled with a write to LX_CTRL register.