logiSDHC - How do I integrate logiSDHC in my design
How do I integrate logiSDHC in my design?

logiSDHC IP can be added into your design from logicBRICKS Project Peripheral Repository.

logiSDHC has configurable register interface which is accessible through OPB, SPLB or AXI4-Lite bus depending on C_REGS_INTERFACE generic.

To achieve better performance DMA functionality should be used, which can be implemented as standard DMA and Xylon DMA. Standard DMA controller is implemented according to the DMA algorithm defined in the SD Host Controller Standard Specification Version 2.00 also called SDMA (Single Operation DMA). Xylon DMA is a custom DMA controller designed to support highspeed DMA bitmap transfers and memory block copy transfers from SD Cards. Both DMA types share the same XMB or AXI4 interface with adjustable burst length. For Xylon DMA there are two additional parameters that need to be set, endianess conversion and row stride. If you use a video controller that reads pixels in, for example, little-endian format, you have to pay attention in which format you have stored your bitmaps. Also, row stride should be the same as that of the video controller.

To ensure proper operation of SD Host controller the user has to provide a 100 MHz sd_base_clk and connect sd_base_lock signal which signals a stable sd_base_clk. If DMA is implemented, user has to provide memory clock and connect it to mclk port which is used for both interfaces, XMB and AXI4. The Host interface is accessed through OPB, SPLB or AXI4-Lite bus which usually provide a register clock signal.

Some advanced software applications with operating systems can save processing time during DMA transfers using interrupts, in that case sd_int interrput port has to be connected to interrupt controller. SD write protect switch (sd_wp), SD card not present (sd_cd_n), SD card not inserted (sd_ci_n), LED indicating that SD Card is in use (sd_led_n) ports are not neccessary for proper operation, but can be beneficial.

SD Card ports (sd_clk, sd_dat, sd_cmd) need to be timing constrained for reliable operation. Please refere to the logiSDHC users manual for more information.

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