logiCVC-ML

logiCVC - How to use triple buffering signals
KBA-01161-V0FRMX
Question
How should logiCVC triple buffering signals be used? What are relative timings of triple buffering signals? What clock is used to drive these signals?
Answer

logiCVC is constantly sampling E_CURRENT_VBUFF and E_SWITCH_VBUFF inputs with MCLK clock input(memory clock). When E_SWITCH_VBUFF high state is detected, logiCVC samples E_CURRENT_VBUFF and asserts E_SWITCH_GRANT along with the associated E_NEXT_VBUFF. External logic should constantly sample E_SWITCH_GRANT signal and when it detects that E_SWITCH_GRANT is high, it should sample E_NEXT_VBUFF and de-assert E_SWITCH_VBUFF. When logiCVC detects E_SWITCH_VBUFF low it de-asserts E_SWITCH_GRANT signal on the next MCLK cycle.

E_SWITCH_VBUFF and E_SWITCH_GRANT signals are used as handshake signals between logiCVC and external logic. This kind of implementation supports switching of buffers between logiCVC and external logic running on synchronous and on asynchronous clocks.

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