In order for logiSDHC to be properly implemented in a design and to be able to achieve optimal operating performance, a specific set of additional constraints is required for the IP. This set of constraints is thoroughly described in logiSDHC user's manual document (see chapter 10. INTEGRATION, section 10.5 Timing constraints).
However, the described syntax is applicable only in Xilinx ISE tool - UCF file syntax.
Here is the equivalent syntax for the specific additional constraints used in Xilinx Vivado tool - XDC file syntax:
set_max_delay -from [get_ports {sdio_cmd_io}] -to [get_cells {*ddr_inst.cmd_i_inst} -hierarchical] 4.000
set_max_delay -from [get_ports {sdio_data_io[0]}] -to [get_cells {*ddr_inst.dat_io_gen[0].dat_i_inst} -hierarchical] 4.000
set_max_delay -from [get_ports {sdio_data_io[1]}] -to [get_cells {*ddr_inst.dat_io_gen[1].dat_i_inst} -hierarchical] 4.000
set_max_delay -from [get_ports {sdio_data_io[2]}] -to [get_cells {*ddr_inst.dat_io_gen[2].dat_i_inst} -hierarchical] 4.000
set_max_delay -from [get_ports {sdio_data_io[3]}] -to [get_cells {*ddr_inst.dat_io_gen[3].dat_i_inst} -hierarchical] 4.000 |