Lane Departure Warning Reference FPGA Design

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The following block diagram presents the reference FPGA design (controller) for the Pedestrian Detection which is used with the logiPD-LDW Development Platform. It is designed using Xylon logicBRICKS IP cores and prepared for use with the Xilinx® Spartan-6 FPGAs. The reference design is fully compatible with Xilinx Platform Studio (XPS) and the EDK implementation tools.

The Lane Departure Warning FPGA - An Example Implementation
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The input image from a camera is demosaiced (Bayer pattern) and stored in memory (full megapixel camera resolution) by the logiBAYER Color Camera Sensor Bayer Decoder IP core.

The logiVIEW Perspective Transformation and Lens Correction Image Processor IP core makes an image transformation from a wide-angled to a bird's eye view of the selected area.

The slave video interface of the logiLMD Lane Marking Detector IP core is connected to the master video interface of the first logiCVC-ML Compact Multilayer Video Controller IP block, which reads out a video frame from memory and streams it to the logiLMD. High level elaboration of logiLMD output is done in software capable to raise a departure warning. The master video interface of the LMD core is connected to the slave video interface of the second logiCVC-ML IP core.

This connection is used to direct the output stream of the logiLMD to one of the video layer of the video controller in order to be able to display the processing result on the screen for validation and demonstration purposes

Xylon offers FPGA design services and can make design changes on request!

Xylon logicBRICKS IP cores for Pedestrian Detection in Automotive and Surveillance Systems

The logiLMD Lane Marking Detector IP core detects the lane markings on the roadway captured from a rear view camera. Its functions include image processing filters, like Gaussian smoothing and Edge detection, and blocks specifically tailored for lane marking detections.

The output of the core is a set of straight lines corresponding to the lane markings.

	The logiLMD core is sourced from Technology Partner eVS embedded Vision Systems Srl.

The presented FPGA SoC architecture can be changed in any feasible way to support the requirements of particular applications. Please contact Xylon if your application requires design changes.

Xylon logicBRICKS IP cores are compatible with Xilinx Platform Studio and the EDK tools. FPGA designers can setup logicBRICKS and Xilinx IP cores through GUI implementation tools, optimize feature sets and control the utilization of FPGA resources, and in a drag & drop fashion, implement Xilinx SoCs without hand coding.

Read More:

- Pedestrian Detection and Lane Departure Warning - Introduction
- Xylon logiPD-LDW Development Platform for Pedestrian Detection and Lane Departure Warning
- The logiPD-LDW Development Platform Package
- Reference logicBRICKS Design for Pedestrian Detection

Lane Departure Warning Reference FPGA Design

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