> 14. September 2011, Zagreb
(Croatia) – Xylon announces new versions of the
logiBAYER Color Camera Sensor Bayer Decoder and the
logiWIN Versatile Video Input IP cores, which now fully support the latest Xilinx® 7 Series FPGAs and the Zynq™-7000 All Programmable SoC.
The logiWIN and the logiBAYER IP cores are designed for video frame grabbing from video cameras (including HD cameras) and other video sources in high-performance embedded real-time video and image processing applications. Multiple logicBRICKS IP core instances enable processing of an arbitrary number of video inputs in a single Xilinx FPGA or SoC device.
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The logiWIN IP core is now ARM® AMBA® AXI4 bus protocol compliant. Besides support for the ITU6565/1120 (PAL and NTSC) and digital RGB inputs, the new logiWIN now supports the YUV 4:2:2 video input format, and includes the YUV2RGB converter and image color enhancement block. Configurable color format ordering allows for easy integrations in Zynq-7000 SoC running Android™ operating system.
The logiWIN Versatile Video Input IP core license fees offered through Xylon's Low-Volume IP Program (LVIP) start at €1,850. For datasheet please CLICK HERE.
Evaluation logiWIN IP core available HERE!
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The logiBAYER IP core is now ARM AMBA AXI4 bus protocol compliant. Besides the support for parallel and LVDS video input streams, the logiBAYER now also supports the AMBA AXI4-Streaming video inputs with input resolutions up to 2048x2048. The logiBAYER supports real-time video scaling down 2x vertically and horizontally, input image cropping, all Bayer pattern combinations...
The
logiBAYER Color Camera Sensor Bayer Decoder IP core license fees offered through
Xylon's Low-Volume IP Program (LVIP) start at €1,850. For datasheet
please CLICK HERE.
Evaluation logiBAYER IP core available HERE!
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Just like all other Xylon logicBRICKS IP cores, the logiWIN and the logiBAYER IP core are fully compatible with the Xilinx ISE® Design Suite. FPGA
designers can setup the IP core configurations through a GUI, optimize
feature sets and control the utilization of FPGA resources, and in a
drag & drop fashion, implement Xilinx SoC without hand coding.
The logiWIN IP core is integrated in Xylon's
free reference design for Xilinx Zynq-7000 ZC702 evaluation kit.
Application examples:
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4-Camera Surround View Driver Assistance system
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Video Multi-Head 360deg Panoramic Camera for surveillance applications