logicBRICKS Design Flow

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logicBRICKS

logicBRICKS Design Flow

Designing with logicBRICKS IP cores is extremely simple. Designers familiar with Xilinx® Vivado® and ISE® Design Suits can start designing with it within minutes, since the logicBRICKS can be used in an exact way as the Xilinx IP cores.

For instructions how to import logicBRICKS IP cores in Xilinx Vivado® Design Suit CLICK HERE!

The IP users get Xylon's IP cores in a format compliant to the Xilinx Platform Studio:

*The IP folder Structure*	The SW driver folder structure

logicBRICKS in the Xilinx Platform Studio IP Catalogue

Click Picture To Enlarge!	The logicBRICKS IP cores must be stored into Xilinx Platform Studio tool's default or user setup Project Peripheral Repository. The Xilinx tool find the Xylon logicBRICKS IPs and display them in the IP catalogue. The figure on the left shows a number of logicBRICKS IP cores setup in the Xilinx Platform Studio IP catalogue, and ready for implementation in the Xilinx FPGA design.

Interfacing logicBRICKS IPs to Xilinx SoC Design

Click Picture To Enlarge!

Xilinx Platform Studio users can simply drag and drop the logicBRICKS IP cores from the IP catalogue into the System Assembly View.

The figure shows an example Xilinx FPGA design utilizing several Xylon IP cores. The logicBRICKS IPs can be connected to the rest of the System-On-a-Chip design by just several mouse clicks.

The figure shows the logicBRICKS IPs connected to the on-chip CoreConnect^TM PLB bus and the Xilinx MicroBlaze^TM soft-CPU.

Setting Up the logicBRICKS IP Parameters

Click Picture To Enlarge!

The logicBRICKS IPs can be simply configured through the Xilinx Platform Studio tool's GUI.

A double-mouse click on the IP in the System Assembly View window opens the IP GUI that allows for parameters changes.
The figure provides a detail of the scrollable parameters list of the logiCVC-ML Compact Multilayer Video Controller. The provided detail illustrates how IP users can easily change i.e., the number of graphics layers supported by the controller, or the pixel color depth.

The GUI also enables an easy access to the IP documentation.

All logicBRICKS IP cores can be parameterized (configured) in the same way. It allows users to setup an exact IP features set prior to a design synthesis. The selected setup directly affects the consumption of the available Xilinx FPGA silicon resources. Removal of unneeded IP features assures a smaller IP implementation and savings on silicon resources.

Upon the definition of internal FPGA architecture and interfaces, the FPGA should be implemented as it is being described by related Xilinx documentation.

logicBRICKS Design Flow

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