HDR ISP framework for multi-camera applications

Key Features

  • Complete HDR ISP video processing framework for multi-channel vision and AI systems
  • Demonstrates logicBRICKS HDR ISP pipeline for parallel processing of four automotive video cameras
  • Fully compatible with Xylon logiISP-ZU-GMSL2 Evaluation Kit based on AMD Zynq™ UltraScale+™ MPSoC
  • Runs on Linux OS, includes logicBRICKS software drivers and demo applications made with AMD Vitis™ Unified Software Platform 2020.2
  • Demonstrates programmable logic savings achieved by multiplexing of ISP functions
  • Includes licensed* Xylon logicBRICKS IP cores
  • Input resolution 1928x1208; output resolution 1920x1080
  • HDMI display output 
  • Jump-starts development and saves valuable design time

* Included are 3-month Xylon seat evaluation licenses for used logicBRICKS IP cores and software.


Xylon offers a complete logicBRICKS IP suite for implementing High-Dynamic Range (HDR) Image Signal Processing (ISP) pipelines in embedded designs based on AMD FPGA, SoC, MPSoC or ACAP programmable devices. HDR ISP pipelines enable crisp camera video under altering and rough lighting conditions in next-generation multi-channel embedded systems for use in automotive, surveillance, medical and similar video and vision AI applications. The reference designs comes as part of the the logiISP-ZU-GMSL2 Evaluation Kit which can be purchased directly from Xylon.

logicBRICKS ISP IP cores enable parallel processing of multiple Ultra HD video inputs in different AMD devices, ranging from the small AMD Artix™ FPGAs to the latest AMD Versal™ Adaptive Computing devices.

The logiREF-MULTICAM-ISP demonstrates these capabilities and shows how, in comparison to simple instantiation of multiple ISP pipelines within a single programmable device, Xylon’s logicBRICKS ISP pipeline allows for tremendous savings of up to 50 % of valuable programmable logic.
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