IP Cores - logiREF-DFX-IDF

logiREF-DFX-IDF Dynamic Function eXchange with Isolation Design Flow

Key Features

  • The complete video design framework to explain & demonstrate the AMD Dynamic Function eXchange (DFX)
  • Fail-safe demo chip designed through the Isolation Design Flow (IDF)
  • Includes the Soft Error Mitigation (SEM) IP Core to demonstrate improved functional safety
  • Design is intended for use with the Xylon logiVID-ZU Vision Development Kit 
  • Demonstrates reconfigurable video filtering on four video channels coming from four 2.3MP HDR cameras
  • Video filters implemented by AMD Vitis™ Video Library HLS functions
  • Prepared for AMD Vivado™ 2021.1 & Vitis Unified Software Platform
  • HDMI™ display output achieved with the AMD HDMI 1.4/2.0 Transmitter Subsystem controlled via Xylon’s DRM kernel driver1
  • Runs on Linux OS and includes logicBRICKS software drivers and demos
  • Documentation and Tech support (e-mail)

1Licensed AMD IP core. Digital code vouchers provided by Xylon to buyers of the logiVID-ZU kit.


Xylon brings the complete design framework to explain and demonstrate the AMD Dynamic Function eXchange (DFX). The DFX enables features swapping by reconfiguring parts of a continually operating programmable FPGA/SoC chip. Designed through the Isolation Design Flow (IDF), included fault-tolerant chip design also showcases AMD functional safety design methodologies for safety-critical applications.

This video design framework is one of the two intended for use with the Xylon logiVID-ZU Vision Development Kit users to quickly utilize the provided hardware platform for development of the AMD Zynq™ UltraScale+™ MPSoC based embedded multi-camera vision systems, while getting familiar with the Dynamic Function eXchange (DFX) feature swapping of continually operating programmable FPGA/SoC chip.

DFX is the ability to deliver new capabilities to silicon on demand, while critical functions remain running. Reconfigurable blocks of programmable logic are dynamically modified by downloading partial bit files.

The demo is based on AMD Zynq™ UltraScale+™ MPSoC programmable device that processes four HD video streams from automotive cameras. Each video channel includes a reconfigurable partition that can be configured by a different video filtering modules defined by provided partial BIT files (3 per RP, total 12).

The framework  includes pre-verified logicBRICKS reference designs for video capture from Xylon cameras and the display output with the RGB overlay under the Linux operating system.

Interested parties should contact Xylon via info@logicbricks.com to inquire about acquiring the logiREF-DFX-IDF Design Framework.

NameLicensePrice (EUR)  
Copyright © 2024 Xylon d.o.o.