Design Description

The complete camera-to-display SoC designs, which use just a fraction of available programmable logic, significantly save the design time. Instead of starting from scratch and having to spend months designing and building a new design framework, the logiADAK-VDF-ZU users can immediately focus on specific vision-based parts of their next SoC design. The designs are prepared for the Xilinx Vivado Design Suite and the SDSoC Development Environment.

CAM-HDMI Design The design implements a single video input, and the display output with the RGB overlay. The video input can be sourced from the Xylon video camera, or through the HDMI input. Video captured by the logiWIN frame grabber IP core is stored in the DDR3 memory, than processed by the inserted Sobel filter (SDSoC video processing example). The filtered video stored in the external memory is displayed by the logiCVC-ML display controller IP core.

FOUR-CAM Design This design implements four parallel video inputs from Xylon cameras and the display output with the RGB overlay. All video inputs are stored in the video memory, and by mean of the on board push buttons, the design user can select each of them for the full screen display output. Video inputs are controlled by the logiWIN Versatile Video Input IP cores, and the video output is displayed by the logiCVC-ML Compact Multilayer Video Controller IP core.

The minimal hardware configuration for the logiADAK-VDF-ZU evaluation is the ZCU102 Evaluation Kit + the Avnet HDMI Input/Output FMC board that enables partial evaluation of the CAM-HDMI reference design.

Read More:

- Introduction
- Design Deliverables
- Quick Start with the Reference Designs