logiREF-VIDEO-ISP-EVK Deliverables

CLICK to open the User's Manual!

What's Included?
Hardware Design Files                                                                        

- Reference design bitstream file
- Reference design for Xilinx® Vivado® Design Suite (2014.4)
- logicBRICKS IP cores*:
    - logiISP Image Signal Processing (ISP) Pipeline
    - logiWIN Versatile Video Input
    - logiCVC-ML Compact Multilayer Video Controller
    - logiCLK Programmable Clock Generator

- Avnet IP cores: FMC Imageon Vita Receiver
- Documentation

*  Xylon provides the evaluation IP cores

Software Design Files_____                                                             

- Standalone (bare-metal) driver with the logiISP driver example and Linux user space driver
- Standalone and Linux user space libraries (OSlib)
- Linux Framebuffer driver for the logiCVC-ML IP core (display controller)
- Documentation


- Linux binaries containing precompiled SD card image for the fastest demo startup:

    - logiISPDemoQt - logiISP demo application with the GUI designed by Qt
    - uboot, dtb(dts), root file system
    - uImage - kernel with framebuffer driver for the logiCVC-ML IP core
    - qt.image - compressed precompiled Qt application framework

- Standalone binaries (zynq_fsbl, logiISP_demo)
- SoC bitstream

Read More:

- logiREF-VIDEO-ISP Description
- Design Requirements
- Quick Start with the Reference Design
- Usage Scenarios - How to use it with the MicroZed Embedded Vision Kit?
Copyright © 2023 Xylon d.o.o.