- Supports Xilinx® Zynq®-7000 AP SoC, 7 series and Spartan®-6 FPGAs
- Provides twelve independent clock outputs: - Six outputs can be dynamically configured
- Six outputs can be configured by generics only
- Input clock frequency range*: - Spartan-6: 19 - 540 MHz
- 7 series: 19 - 1066 MHz
- Output clocks frequency range*: - Spartan-6: 3.125 - 400 MHz
- 7 series: 6.25 - 741 MHz
- Configurable registers interface compliant to: - ARM AMBA AXI4-Lite
- CoreConnect(TM) PLBv46
- SW support for Linux and Microsoft® Windows® EC OS
- Available for Xilinx Vivado® IP Integrator and ISE® Platform Studio
* Depending on the used device's speed grade
The logiCLK is a programmable clock generator logicBRICKS IP core with twelve independent and fully configurable clock outputs. While six clock outputs can be fixed by generic parameters prior to the implementation, the other six clock outputs can be either fixed by generics or dynamically reconfigured in a working device. The Dynamic Reconfiguration Port (DRP) interface gives system designers the ability to change the clock frequency and other clock parameters withe the design is running by mean of a set of memory-mapped PLL configuration and status registers.
Xylon uses the logiCLK IP core in free and pre-verified Graphics Processing Unit (GPU) reference designs prepared for popular Zynq-7000 AP SoC based development kits, i.e. the logiREF-ZGPU-ZED design for the ZedBoard™ development kit from Avnet Electronics Marketing. This graphics engine reference design uses the logiCLK IP core as a programmable source of a video clock signal, which must be run-time changed to support different standard display (video) resolutions. Xylon’s software drivers (Linux, Microsoft Windows Embedded Compact) for graphic logicBRICKS IP cores include support for the logiCLK IP core. The drivers accept the input clock frequency and desired output frequencies as input parameters, and automatically program the logiCLK configuration bits.