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|Xilinx® Base TRD reference design uses Xylon's logiCVC-ML advanced display graphics controller IP core that enables an easy video and graphics integration into embedded systems with the Xilinx Zynq®-7000 All Programmable SoC and all Xilinx FPGA families.
This display controller supports up to 5 layers with configurable size, position and pixel color depth, three types of alpha blending, different video output formats...
logiCVC-ML Features used in the Base TRD:
|Extensive logiCVC-ML display controller IP core software support includes SW drivers for: Linux®, Android™ and Microsoft® Windows® Embedded Compact 7. A number of Xilinx partners who provide BSP for different operating systems supports Xylon logicBRICKS IP cores for graphics.
Graphics logicBRICKS - OS Support
|Multi-Layering: logiCVC-ML display controller IP core enables easy mixing and blending of multiple video inputs with the HMI. Xilinx Base TRD shows the HMI blended over the processed video input (user controlled level of transparency). The blending is HW accelerated and need no CPU time!
The IP core also implements means for video input and output synchronization.
|Software support: The demo runs on the Linux OS. Xylon provides Linux drivers for the logiCVC-ML IP core as open-source software. Click HERE to learn more.
Standard Linux support allows for an easy work with the QT cross-platform application framework for developing application software with a graphical user interface (GUI).
|Memory Bandwidth Management: The logiCVC-ML IP core can be configured in many different ways to increase performances, save utilized programmable logic resources and efficiently utilize memory bandwidth that is always critical design parameter in video and image processing applications.
For example, the HMI layer in the Base TRD is:
- sized to roughly 1/3 of the HD resolution, which saves on the required memory bandwidth
- positioned at the bottom of the screen with no need for complex DMA programming
- configured to use 16-bit pixel color depth, which saves 1/2 of the memory bandwidth in comparison
to the 24-bit video layer
- configured to use simple Layer Alpha Blending because there is no need for more sophisticated
Pixel Alpha or Color Look-Up Table (CLUT) blending modes.
|IP Quality and Maturity: Xylon released the logiCVC-ML Compact Multilayer Video Controller IP core for the first time in the year 2001. Since that time it has been continuously maintained and upgraded to the latest Xilinx All Programmable FPGA and SoC families, implementation tools, operating systems... Each new IP core's release is carefully verified in thousands of different configurations to assure the best user experience possible. The logiCVC-ML has been widely used in different end markets and applications.
|Easy of Use: Xylon logicBRICKS IP cores require no skills beyond general Xilinx tools knowledge, and can be used in a same way as Xilinx IP cores in Vivado IP Integrator or Xilinx Platform Studio implementation tools.
- Design Description
- Design Requirements
- Quick Start with the Reference Design
Xylon distributes the Xilinx Base TRD for the ZedBoard from Avnet Electronics Marketing with permission from Xilinx, Inc.