ACAP HDR Image Signal Processing Framework

The logiREF-ACAP-MULTICAM-ISP ACAP HDR Image Signal Processing Framework is intended to showcase a complete logicBRICKS IP suite implementation of High-Dynamic Range (HDR) Image Signal Processing (ISP) pipeline in an embedded design based on AMD-Xilinx ACAP programmable devices. The HDR ISP pipeline enables crisp camera video under altering and rough lighting conditions in next generation multi-channel embedded systems for use in automotive, surveillance, medical, aerospace and similar video and vision AI applications.

Key IP cores, the logiISP-UHD ISP and the logiHDR pipelines, support parallel processing of multiple video inputs, resolutions up to 7680x7680 (including the popular 4K2Kp60 video resolution), merging of two or three exposures, parallel pixel processing and different pixel formats. These IP cores for programmable logic implementations are supplemented with AWB and AE software libraries that use video statistics data collected at video inputs, software drivers, demo applications, reference SoC/ACAP designs, and bit-accurate C models.

MULTICAM-ISP Design The design framework implements three parallel video inputs from three 7.4Mpix Leopard Imaging IMX424 GMSL2 video cameras and the UHD display output. All video inputs are stored in the video memory, and by mean of on-board push buttons, the user can select each of them for the single camera or all cameras full screen display. Video inputs are controlled by the logiWIN Versatile Video Input IP cores, and the video output is displayed by the logiCVC-ML Compact Multilayer Video Controller IP core.