The logiREF-DFX-IDF Design Framework includes pre-verified and licensed Xylon logicBRICKS IP Cores. It is prepared for the 2021.1 versions of the AMD-Xilinx Vivado ML Design Suite & AMD-Xilinx Vitis Unified Software Platform.
This design implements four parallel video inputs from Xylon cameras and the display output with the RGB overlay. All video inputs are stored in the video memory, and by mean of the on board push buttons, the design user can select each of them for the full screen display output. The user also has the option to start the Error Injection demo where the design framework injects an single error into the configuration memory and then proceeds to fix it on the fly through the use of the SEM IP Core.
For a more detailed overview of the how the various parts of the design framework are interlocked, please refer to the Block Schematic below, which can also be found in the logiREF-DFX-IDF Datasheet and User's Manual.
Video inputs are controlled by the logiWIN Versatile Video Input IP cores, and the video output is displayed by the logiCVC-ML Compact Multilayer Video Controller IP core. All Xylon IP Cores are highly configurable and can be evaluated independently through our Low Volume IP Evaluation Program.