which is based on the AMD Zynq™ UltraScale+ MPSoC. This hardware platform is optimized for embedded multi-camera vision systems. However, the demonstrated principles, techniques and design solutions can be easily adapted for different application spaces and other AMD programmable devices.The design framework includes the MPSoC design that processes HD video channels from four 2.3MP automotive cameras.
Each video channel includes a reconfigurable partition (RP) of programmable logic that can be re-configured by different video filtering modules defined by a set of three partial BIT files provided for each RP. Processed video streams are displayed on the HDMI monitor attached to the AMD evaluation board. Demo users can choose between a single camera view and an all cameras tiled view. Also, each video channel can be independently processed by a reconfigurable Sobel filter, CCM Green, or no filter (RGB view). The demo also includes video error injection and its correction by an integrated SEM IP core. Dynamic Function eXchange (DFX) is the ability to deliver new capabilities to silicon on demand, while critical functions remain running. In other words, the DFX enables features swapping by reconfiguring parts of a continually operating programmable FPGA/SoC chip. The logiREF-DFX-IDF Design Framework is specifically prepared for evaluation on the GMSL2 version of the logiVID-ZU MPSoC Vision Development Kit.
The Isolation Design Flow (IDF) enables designers to develop fail-safe single chip solutions that confine the fault to a single region of the chip – without affecting more than one function. It enables implementation of security- or safety-critical designs. The chip design is immune to single point failures (except power and ground). Isolated Regions can be defined as RP reprogrammable partitions to confine faults on a single chip function (Region).Flexibility of the existing design is taken one step further by utilizing Dynamic Function eXchange (DFX) and Isolation Design Flow (IDF) solutions together to allow modifications of operating FPGA design by loading partial BIT files defining video filtering examples. Demonstrated video filters are built by Vitis Vision Library HLS functions.Another layer in this drive towards functional safety is the implementation of the Soft Error Mitigation (SEM) IP Core in the design.
SEM provides the ability to detect and correct single errors in the configuration memory of the programmable logic, as well as the detection of multiple configuration errors in which case it triggers reconfiguration for the affected isolated chip region. The IP core is using ECC and CRC values associated with the configuration bitstream.
Xylon offers design services, consultancy and other forms of support for any developer looking to implement DFX or IDF into their products. For more information regarding this, please contact Xylon at
info@logicbricks.com .