The logi3D Scalable 3D Graphics Accelerator IP Core - Use Scenarios

Use Scenario 1: logi3D in Xilinx® Zynq®-7000 All Programmable SoC

Xylon's logi3D Scalable 3D Graphics Accelerator IP core is designed primarily for use in the Xilinx Zynq-7000 AP SoC. The IP core is AMBA® AXI4 compliant and can be simply interconnected with other IP cores implemented in the Zynq-7000 programmable logic. Two ARM® Cortex™-A9 processors from the Zynq-7000 processing system run the operating system, OpenGL® ES 1.1 library and graphics and other software applications. The logi3D can use the ARM NEON™ coprocessor for additional performance in 3D graphics rendering. The tight integration of the processing system with the programmable logic enables very high speed data flow between the processors and soft-IP accelerators in the programmable logic, as well as the usage of a common memory device.


Use Scenario 2: logi3D in Xilinx FPGA controlled by an External Processor

The logi3D Scalable 3D Graphics Accelerator can be implemented in several Xilinx FPGA families. Such ASSP+FPGA systems require an external processor for a full  3D graphics implementation, and a bridge between the processor's external bus and  the internal FPGA ARM® AMBA® AXI4 bus system. The FPGA works as a companion chip to the external processor - Click to learn more about Xylon Companion Chips.

Product is based on a published Khronos specification, and is expected to pass the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.