The logiJPGD Multi-Channel Motion JPEG Decoder is JPEG standard Baseline DCT compliant decoder IP core for still image and video decompression applications on AMD All Programmable SoC and FPGA devices. This IP core is specially designed for video over IP applications where the video payload from multiple video channels comes in a non-guaranteed order and encapsulated in network frames, i.e. the Ethernet UDP packets. With a very low burden on the system CPU, it enables highly automated video decoding while respecting the accurate order and the exact frame rates of input video channels.
The logiJPGD is fully embedded into the AMD Vivado™ IP Integrator to hide a complexity from the end-user and to make its integration with the on-chip AMBA AXI4 bus easy. The provided logiJPGD software driver simplifies the IP core programming. The logiJPGD reference design, which is on request available from Xylon, can be used as a starting point to evaluate and develop AMD-based MJPEG video processing embedded systems. Please submit your request for evaluation at email@example.com