IP Cores - logiJPGD

Multi-Channel MJPEG Decoder

Key Features

  • Supports AMD Zynq™ UltraScale+ MPSoC, Zynq™ 7000 AP SoC and Series 7 FPGA families
  • Compliant with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard
  • Works with up to 4 HD video inputs simultaneously
  • Keeps up the exact frame rates to ensure smooth playback
  • Video input/output resolutions up to 2048x2048
  • Pixel formats: YUV 4:2:0 and YUV 4:2:2
  • IP deliverables include software driver, documentation and technical support
  • Reference design for the AMD ZC702 Evaluation Kit available on request
  • Available for AMD Vivado™ IP Integrator and ISE® Platform Studio


The logiJPGD Multi-Channel Motion JPEG Decoder is JPEG standard Baseline DCT compliant decoder IP core for still image and video decompression applications on AMD All Programmable SoC and FPGA devices. This IP core is specially designed for video over IP applications where the video payload from multiple video channels comes in a non-guaranteed order and encapsulated in network frames, i.e. the Ethernet UDP packets. With a very low burden on the system CPU, it enables highly automated video decoding while respecting the accurate order and the exact frame rates of input video channels.

The logiJPGD is fully embedded into the AMD Vivado™ IP Integrator to hide a complexity from the end-user and to make its integration with the on-chip AMBA AXI4 bus easy. The provided logiJPGD software driver simplifies the IP core programming. The logiJPGD reference design, which is on request available from Xylon, can be used as a starting point to evaluate and develop AMD-based MJPEG video processing embedded systems. Please submit your request for evaluation at info@logicbricks.com.
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