IP Cores - logiMLB

Media Local Bus Interface

Key Features

  • Adds MOST® connectivity to Xilinx® FPGAs/SoC
  • Licensed MediaLB® technology from SMSC®
  • Compliant with the MLB Specification Version 4.2
  • Supports 3-pin and 6-pin interface to INICs
  • Supported transport methods: synchronous, asynchronous, control and isochronous
  • Supports Xilinx Spartan®-6 FPGA family, 7 series and Zynq-7000 All Programmable SoC

Description

The logiMLB IP core from Xylon's logicBRICKS IP library supports implementation of the SMSC's Media Local Bus (MediaLB) inter-chip communication technology in Xilinx FPGA/SoC and an efficient transport of multimedia data through SMSC's Intelligent Network Interface Controllers (INICs) onto a Media Oriented System Transport (MOST) network. The MOST networks are infotainment backbones in many cars and de facto industry standard for automotive multimedia networking of high-bandwidth audio, video and control information or network data.

The logiMLB Media Local Bus Interface IP core complies with the latest MLB Specification version 4.2, and works with all MOST network generations - MOST25, MOST50, and MOST150. It supports a 3-pin single-ended MediaLB connection with up to 1024xFs, and a 6-pin differential connection with up to 4096xFs. The logiMLB provides internal buffering and support for up to 63 TX and RX channels.
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