- Supports AMD-Xilinx Zynq®-7000 SoC, Zynq UltraScale+ MPSoC and 7-series FPGAs
- Lossless on-the-fly video decoder to Motion JPEG (MJPEG) video stream
- Compliant with the Annex H of the ISO/IEC 10918-1 JPEG Standard
- Lossless process based on the Huffman coding algorithm
- Video input/output resolutions up to 4096x16384
- The IP Core supports video input frames with one color component and precision up to 12 bits
- IP deliverables include software driver, documentation and technical support
- Xylon also offers the logiJPGE-LS Lossless MJPEG Encoder IP Core
- Reference design for the AMD-Xilinx ZC102 Evaluation Kit available on request
- Deliverables prepared for AMD-Xilinx Vivado® Design Suite 2021.1
The logiJPGD-LS Motion JPEG (MJPEG) Decoder is Xylon’s logicBRICKS IP core for still image and video decompression applications on AMD-Xilinx MPSoC, SoC, and FPGA devices. It includes all logic blocks necessary for quick implementations of ARM AMBA AXI4 streaming-based FPGA/SoC architectures and enables on-the-fly JPEG decompression of input video with resolutions up to 4096x16384 (including full HD video at 60 fps – 1080p@60).
At the center of the logiJPGD-LS IP core is a decoder block, based on the Huffman coding algorithm. It works with the color component precision up to 12 bits and supports standard JPEG headers. The logiJPGD-LS IP Core supports decompression of JPEG LS frames with one color component, the so-called color plane. A full multi-color video decompression requies division of JPEG encoded multi-color videos (i.e. Bayer, YUV, RGB) in separated JPEG LS frames per color component – color planes. One logiJPGD-LS IP core can sequentially decompress all color planes to generate multi-color video output. Alternatively, multiple logiJPGD-LS IP cores instantiated in a parallel can decompress all input color planes at once.
In typical IP applications, a previously encoded (compressed) MJPEG video is decoded (de-compressed) and transferred to the IP core’s output. The de-compressed video can be further processed by the next block in the video pipeline, or with an additional Xilinx IP such as AXI Video DMA, directly stored to off-chip memory. The logiJPGD-LS IP Core works smoothly with Xylon's logjJPGE-LS Lossless MJPEG Encoder IP Core, as well as other lossless MPJEG encoders compatible with the Annex H of the ISO/IEC 10918-1 JPEG Standard. Xylon also offers a pair of lossy MJPEG compression (logiJPGE) and decompression (logiJPGD) IP cores which give the user the ability to tune the level of compression used.
Please submit your request for evaluation at email@example.com .