IP Cores - logiHSSL

Slave HSSL Controller

Key Features

  • Supports Xilinx® UltraScale™, UltraScale+™ FPGA and UltraScale+ Zynq® MPSoC
  • Supports Xilinx Zynq-7000 SoC and 7 Series FPGAs
  • Infineon High Speed Serial Link (HSSL) slave device
  • Up to 320 Mbaud/s baud rate
  • ARM® AMBA® AXI4-Lite bus compliant as a slave
  • ARM AMBA AXI4 bus compliant as a master
  • 3 GB of addressable space covers access to:
  • - FPGA fabric registers and RAM
    - PS register space and On-Chip Memory (OCM)
    - On-board linearly addressable Flash memory
    - On-board DDR memory
  • logiHSSL-ZU development starter kit available from Xylon
  • Fully embedded into Xilinx Vivado® Design Suite


The logiHSSL IP core enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and Xilinx SoC (System-on-Chip), MPSoC (MultiProcessor SoC) and FPGA (Field Programmable Gate Arrays) devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baudrates of up to 320 Mbaud at a net payload data-rate of up to 84%.

The logiHSSL IP core allows system designers to combine functional safety and security provided by AURIX™ with the wide range of functional possibilities brought to the table by the Xilinx devices. Linked devices can access and control each other’s internal and connected resources through the HSSL. The logiHSSL IP is prepared for the Xilinx Vivado Design Suite to enable quick and efficient resource implementations in the latest Xilinx All Programmable devices for use in the embedded systems that meet the highest safety standards.

Jump-start your design with the  logiHSSL-ZU FPGA HSSL Starter Kit that provides all HW and SW parts needed to quickly start the new HSSL design. 
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