Hardware Platforms - logiHSSL-ZU

FPGA HSSL Starter Kit

Key Features

  • Combines Infineon's AURIX™ microcontroller and Xilinx's UltraScale+ MPSoC programmable device
  • Integrates Infineon High Speed Serial Link (HSSL) optimized for Xilinx FPGA implementations
  • Includes complete reference design with the evaluation logiHSSL IP core
  • Design is prepared for Xilinx Vivado® Design Suite
  • Linked devices can access and control each other's resources
  • Complete hardware platform includes:
    - 1x Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit
    - 1x Infineon Aurix Evaluation Board Kit KIT_A2G_TC397_S_TRB
    - 1x Xylon FMC board for cable connection
    - 1x FireWire cable
  • Documentation and tech support (e-mail)

Description

The logiHSSL-ZU FPGA HSSL Starter Kit designs provides system designers with everything they need to quickly interconnect the Infineon’s AURIX™ microcontrollers with the Xilinx All Programmable FPGA and SoC devices via the Infineon High Speed Serial Link (HSSL). Combinations of these devices solve the rising safety and performance requirements in emerging automotive and industrial designs.

Kit deliverables include the complete reference design built around the logiHSSL Slave HSSL Controller IP core, which enables the linked devices to access and control each other's internal and connected resources through the HSSL. All logicBRICKS IP cores are prepared for the Xilinx Vivado Design Suite and come with 1-month evaluation IP licenses, documentation and support.

The logiHSSL IP core enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and Xilinx SoC (System-on-Chip), MPSoC (MultiProcessor SoC) and FPGA (Field Programmable Gate Arrays) devices via the Infineon High Speed Serial Link (HSSL). This serial link supports baudrates of up to 320 Mbaud at a net payload data-rate of up to 84%.

The logiHSSL-ZU FPGA HSSL Starter Kit will be available in March 2019. For more information, please contact please Contact Xylon Support

Zynq-7000 SoC Demo Design

- The HSSL IP core (HSSL #0) can access register sets of all SoC IP cores through the PS 7 AXI Interconnect
- The HSSL control module can access internal HSCT, HSSL and BCU register space through the same AXI infrastructure
- HSSL IP core can access PS register space and on-board memory through GP and HP AXI3 ports on PL-PS interface
- Programmable logiCLK IP core changes clocking on the fly and enables HSSL IP core setup to the required baud rate


Pricing
NameLicensePrice (EUR)  
logiHSSL-ZU
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