IP Cores - logiMEM_arb

SDRAM Memory Controller and Arbiter

Key Features

  • Try Before Buy - No cost and no obligation!
  • Designed for Xilinx® Spartan®-6 FPGA
  • Supports DDR/DDR2/DDR3/LPDDR
  • Utilizes integrated Xilinx Memory Controller Blocks (MCB)
  • Achievable memory bandwidths of up to 6.4 GB/sec
  • Supports total of 16 ports and up to 8 simultaneous memory accesses
  • Supports: AMBA® AXI4, CoreConnect PLB, Xilinx Cache Link XCL, Xilinx Native Port Interface NPI, and Xylon Memory Bus (XMB)
  • Can support special memory interfacing requirements on request


The logiMEM_arb Memory Controller and Arbiter IP core, from Xylon logicBRICKS IP library, allows users to easily connect different SDRAM memories to the FPGA chip. Designed specially for Xilinx Spartan-6 FPGAs, the IP core fully utilizes Xilinx's embedded block multi-port memory controller hard IP cores (MCB) and enables the maximum achievable memory bandwidths of up to 6.4 GB/sec.

The logiMEM_arb memory controller IP core supports up to 16 ports for on-chip processor and peripheral IP connections, and by means of memory interleaving, simultaneous memory accesses of up to 8 IP cores. The simultaneous memory accesses greatly improves memory bandwidth utilization of external SDRAM devices. The IP core can use all available MCBs within the certain Xilinx Spartan-6 chip.

Controller’s ports for IP connections are very programmable. Users can configure the ports to support different on-chip bus standards: AMBA® AXI4, CoreConnect Processor Local Bus (PLB), Xilinx Cache Link for Xilinx’s soft-CPU MicroBlaze(TM) cache interface, Xilinx Native Port Interface (NPI) and Xylon Memory Bus (XMB).
NameLicensePrice (EUR)  
logiMEM_arb 1 year license 1,020.00
logiMEM_arb 2 years license 1,840.00
logiMEM_arb 3 years license 2,450.00
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