IP Cores - logiSLVDS_RX

Camera Sub-LVDS Receiver

Key Features

  • Supports AMD Zynq 7000 Adaptive SoC and Series 7 FPGAs
  • Enables easy interfacing of Ultra HD CMOS image sensor
  • Supports Sub-LVDS interface and recognizes major Sony IMX image sensor sync codes
  • Fully compatible with the Sony IMX274 and IMX290 CMOS image sensors
  • Xylon supports modifications and adoption for other sensors through design services
  • Supported number of bus channels (diff. pairs): 4, 6, 8, and 10
  • Supports Raw Bayer 10/12-bit video input and 8/10/12-bit video output
  • Enables parallel processing of 1, 2 or 4 pixels per clock
  • Generates SYNC signals for sensors and marks different exposures in the HDR video input
  • Video Input and output are ARM® AMBA® AXI4-Stream protocol compliant
  • Optional registers are AMBA AXI4-Lite protocol compliant
  • Available for the AMD Vivado™ IP Integrator


The logiSLVDS_RX IP core enables easy interfacing of ultra high resolution Sony CMOS image sensors to image signal processing pipelines and application processors implemented in AMD All Programmable devices. High speed data transfers are supported by the Sub-LVDS differential interface, which is a reduced voltage form of the LVDS signaling. The IP core can be configured to support up to ten (10) interface channels (differential pairs). It performs data deserialization, recognizes camera sync codes, optionally generates HSYNC and VSYNC signals required by the sensor, buffers pixels to decouple image sensor and the internal SoC bus, and outputs the video data packaged in compliance to the AXI4-Stream interface. It can also mark two different exposure video lines when used with HDR image sensors. In order to support the highest possible input video resolutions, the logiSLVDS_RX IP core can be configured for parallel processing of 2 or 4 pixels per clock.
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